module carry_save_mult(LEDR, SW, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7);
	// Size of multiplier (n*n)
	parameter n = 8;

	// Input and outputs
	input [15:0] SW;
	output [17:0] LEDR;
	output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
	
	// Wires
	wire [7:0] A, B;
	wire [15:0] result;
	wire [7:0] C [7:0], S [7:0];
	
	// Static assignments
	assign A = SW[15:8];
	assign B = SW[7:0];
	
	// BCD modules
	BCD(SW[15:12],HEX7);
	BCD(SW[11:8],HEX6);
	BCD(SW[7:4],HEX5);
	BCD(SW[3:0],HEX4);
	
	BCD(result[15:12],HEX3);
	BCD(result[11:8],HEX2);
	BCD(result[7:4],HEX1);
	BCD(result[3:0],HEX0);
	
	genvar i,j;
	
	generate
		for (i = 1; i <= n-1; i = i+1) begin:addrow
			for (j = 1; j <= n-1; j = j+1) begin:addcol
				if (i==1)
					full_adder(A[i]&B[j-1], A[i-1]&B[j], 1'b0, C[i][j], S[i][j]);
				else if (i!=1 & j==n-1)
					full_adder(A[i-1]&B[j], A[i]&B[j-1], C[i-1][j], C[i][j], S[i][j]);
				else if (i!=1 & j!=n-1)
					full_adder(S[i-1][j+1], A[i]&B[j-1], C[i-1][j], C[i][j], S[i][j]);
			end
		end
	endgenerate
	
	carry_lookahead_adder({A[7]&B[7],S[7][7:1],S[6][1],S[5][1],S[4][1],S[3][1],S[2][1],S[1][1]},{C[7][7:1],7'b0},result[15],result[14:1]);
	assign result[0] = A[0]&B[0];
endmodule 